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SPCA500A Digital Camera Chipset
SPCA500A
05 Oct, 1999
Ver. 0.2
1999/10/05 Ver. 0.2
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Preliminary
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1. General description
SPCA500A Digital Camera Chipset
SPCA500A provides a single chip solution for dual-mode digital camera. It includes image sensor interface, image processor, storage controller, image compression engine, USB interface and a built-in micro controller. SPCA500A supports both CCD image sensors and CMOS sensors. The sensor resolution ranges from VGA to XGA.
2. Feature
T Dual mode operation. Support Digital Still Camera mode and PC Camera video mode. T Still image size 640x480 or 1024x768 T Video image size 640x480, 320x240, 160x120. T Support both VGA-type and XGA-type CCD sensor :
VGA - SHARP LZ24BP, SONY ICX098AK, PANASONIC MN3777 XGA - SONY ICX204AK, PANASONIC MN3778 T Support VGA CMOS sensor : HP HDCS-2000, PhotoBit PB320, Hyundai HV7131B, Omnivision QV7610, Pixart PAS002 T Support CDS/AGC/AD : Hitachi HD49323, Sharp IR3Y38M, EXAR XRDxx, Panasonic AN2104FHQ, ADI AD9803. T Anti-flicker (60Hz/50Hz) function in Video mode T Programmable polarity of all Timing control signals for CCD and CDS/AGC/ADC T Support AE/AWB function. T Support 16 M SDRAM and 64M (2-bank and 4-bank) SDRAM. T Store the compressed images in the Flash memory or in the DRAM. T JPEG-based compression algorithm. T Programmable Quantization table T Support 2 M, 4 M & 8M x 8 bit NAND Flash memory for storage image/audio data. T Hardware generated ECC code for (flash) memory access T Support a digital interface to access AC-97 device. T Support USB bus with built-in transceiver. T Six USB pipes supported, including default Control pipe, Isochronous pipe, Bulk-in pipe, Bulk-out pipe, Interrupt pipe and Audio pipe. T Build-in 8032 micro-controller and 4K byte internal data SRAM T Synchronous Serial Interfaces to control CMOS sensor T 128pins QFP package.
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3. Function description 3.1. Block diagram
CDS/AGC DRAM
SPCA500A Digital Camera Chipset
USB Bus
CDSP
DRAM controller
USB/Flash memory/Audio controller
Flash memory
TG
JPEG
8032
CCD sensor & CDS/AGC
gpio
AC-link
3.2. TG
The TG unit provides all the control signals and synchronization signals to either external devices (CCD, CDS/AGC/ADC) or internal blocks. This unit is very flexible and can be programmed through the USB interface. Programming value which control the frame rate and exposure time (ref. MHCK, MCKSRC, PLL_DIV_3, PLL_DIV_6, PLL_HF, SD and RATE) will not take effect until the next frame starts. The CDS/AGC/ADC interface control registers are also generating the serial transfer at the next frame. Other control registers take effect just when they are programmed. The supported CCD sensors include SHARP LZ24BP, SONY ICX098AK, Panasonic MN3777, SONY ICX204AK and Panasonic MN3778. The CDS/AGC/ADC interface are designed for SHARP IR3Y38M, Hitachi HD49322/323BF, ADI AD9803, EXAR XRD44L61 and Panasonic AN2104FHQ. Others that have the similar serial interface are also supported. To support 30 frame/sec video mode, the TG adopts two different pixel rates for different CCD sensors. 12 MHz pixel rate is used for VGA-type CCD sensor, and 19.2 MHz pixel rate is used for XGA-type CCD sensor.
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SPCA500A Digital Camera Chipset
The serial programming sequence for the CDS/AGC/ADC interface is as follows. First, users set data to PRG_MODE and CDSBITS as the programming mode, then users write serial data bytes into CDS_REG1, CDS_REG2 through CDS_REGA. Every writing of CDS_REGA will schedule a serial data transfer at the next frame start. Bits that exceed the number of CDSBITS will be discarded. Each data byte is shifted out in MSB-first manner. Several serial interfaces are defined as follows : PRG_MODE=0 Only SCK, SDATA, no SLOAD signal needed. One dummy SCK pulse cycle to lead actual data. Every rising SCK to latch SDATA. The falling edge of SCK which latches SDATA at high denotes the end of transfer. (eg. SHARP IR3Y38M) Three signals are used. SCK starts to fall after SLOAD is low. Every rising SCK to latch SDATA. (eg. Hitachi HD49322BF) Three signals are used. SCK starts to rise after SLOAD is low. Every rising SCK to latch SDATA. (eg. ADI AD9803, EXAR XRD44L61) Three signals are used. Every rising SCK to latch SDATA. SLOAD stays low during SCK is clocking, then one pulse of SLOAD denotes the end of transfer. (eg. Panasonic AN2104FHQ)
PRG_MODE=1 PRG_MODE=2 PRG_MODE=3
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V-Rate timing (still image mode)
SPCA500A Digital Camera Chipset
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V-Rate timing (video mode)
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3.3. CDSP
SPCA500A Digital Camera Chipset
The CDSP performs optical black compensation, color separation, color correction, edge enhancement, gamma correction, white balance measurement and exposure measurement. The functional block is shown.
cc d d ata
o ptic al bla ck co m p ensa tion
co lo r sep aratio n lin e m e m o ry co lo r co rrectio n
rgb
rgb to y uv m atrix tra nsfo rm
Y UV
cp u interface
w in d ow co n trol
av erag e lum in a nc e
cp u a d dr cp u d ata
d ata f low co n tro l flo w
There are many parameters could be customized by users. Each parameters is 8-bit which are described in section 6.2. All of the customized parameter value are updated at the beginning of one frame. The parameter of the white balance gain denotes the unsigned representation, the integer part 3-bit and the decimal fraction part 6-bit (ref. Addr 0x8151 to Addr 0x8155). The parameter of the color correction denotes the 2*s compliment representation, the sign bit, the integer part 3-bit and the decimal fraction part 4-bit (ref. Addr 0x8108 to Addr 0x8110). The operation range is from 7.9375 to -8. The color correction performs the following matrix operation : Rout = A11 * Rin + A12 * Gin + A13 * Bin Gout = A21 * Rin + A22 * Gin + A23 * Bin Bout = A31 * Rin + A32 * Gin + A33 * Bin The parameter of the white balance offset denotes the 2's compliment representation, the integer part 7-bit and no the decimal fraction part(ref. Addr 0x8111 to Addr 0x8114). There are six windows for exposure measurement and five windows for white balance measurement. The window start point (X,Y) is at the most upper left corner. The X is the horizontal axis and equals to 4 times the parameter value. The Y is the vertical axis and equals to 4 times the parameter value except window 5. The Y of the window 5 is 2 times the parameter value. The window 1 to the window 4 are the 128x128 pixels. The window 5 and the window 6 are the 256x256 pixels. All of the window's position is programmable except the window 6.
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SPCA500A Digital Camera Chipset
The average luminance denotes with dynamic range [0~255] (ref. Addr 0x8121 to Addr 0x8126). The average (R-G)/(B-G) means the average value of (R-G)/(B-G) in the specified window that the luminance value is greater than the low luminance threshold(Addr 16) and less than the high luminance threshold(Addr 15). It denotes with dynamic range [-128~+127]. However, the actual average (RG)/(B-G) value in the CCDSP module is 2 times the parameter value (ref. Addr 0x8127 to Addr 0x8130). The spot count value means the total pixel number in the specified window that the luminance value is greater than the luminance threshold and less than the high luminance threshold . It is a reference value for auto white balance (ref. Addr 0x8133 and Addr 0x813C). The look-up table is a programmable function for gamma correction. There are 3 look-up tables for R,G,B, respectively. Each look-up table have 16 segments. (ref. Addr 0x8190 to Addr 0x81C2) The USB burst-read can be performed by reading Addr 0x817D, Addr 0x817E and Addr 0x817F respectively. The burst-read sequence is the window1, window2, window3 and window4. The USB burst-write can be performed by writing Addr 0x817C. The burst-write sequence is the window1 X, window1 Y, window2 X, window2 Y, window3 X, window3 Y, window4 X and window4 Y. The parameter of brightness denotes 2's complement(Addr 0x8167) and the dynamic range [-128 ~ +127]. The real value of brightness equals 2 times this parameter. The parameter of contrast(Addr 0x8168) include 1 integer bit and 5 fraction bits. It denotes with dynamic range [0 ~ 1.96875]. The parameter of saturation(Addr 0x8169) include 1 integer bit and 5 fraction bits. It denotes with dynamic range [0 ~ 1.96875]. The parameter of hue(Addr 0x816A and 0x816B) include 10 integer bits. It denotes with dynamic range [0 ~ 719]. Each step represents 0.5 degree.
3.4. JPEG
JPEG-based compression algorithm is adopted in the SPCA500A. The Quantization table is programmable via the JPEG register set. The JPEG compression unit accepts YUV data from the DRAM controller and outputs the VLC code to the DRAM controller. In the DSC mode, the data is YUV422 format. In Video mode the data is YUV420 format. MCU (8x8 minimum coding unit)
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SPCA500A Digital Camera Chipset
sequence in DSC mode is YYUV and YYYYUV in video mode. The JPEG compression unit also generates the thumbnail image for the DRAM controller. The thumbnail image is constructed by the DC-value of each MCU. The size of the thumbnail image in VGA mode is 80 x 60 and 128 x 96 for the XGA mode.
3.5. DRAM interface SPCA500A uses DRAM as the frame buffer to hold the incoming image. The DRAM is also used as temporary compression buffer for the compression unit. Optionally, if the DRAM is chosen to be the storage element of the camera (instead of flash memory), it can be used to store the compressed image and thumbnail image. Refer to the DRAM controller register for the different DRAM type and DRAM size settings. The maximum size supported is 4Mega words. Because the different type of DRAMs have different number of bits for their column address and row address, it is more convenient for the DRAM controller to provide a virtual addressing space for the application. The virtual column address is 10-bit long and row address 12-bit long. This addressing mechanism yields the maximum space of 4-Mega words. However, if only one 16-Mega bit SDRAM is used in the application. The addressing space is only 1 Mega word. Normally, if the application uses flash memory to store the compressed images, there is no need of DRAM with size over 1-Mega words. If the DRAM is chosen to be the storage, then the application may add more DRAM to increase the number of images that can be stored in the camera. The operation of the DRAM controller is different in the DSC mode and in the Video mode : In the DSC mode : The DRAM controller goes through capture, compress, and saving stage step by step according to the micro-controller commands. The image size of the DSC mode is fixed at 640x480 for VGA-type CCD sensor, and 1024x768 for XGA-type CCD sensor. In the Video mode : The DRAM controller operates a bit more automatically. After the input image accumulates to enough amount for the compression unit, it sends the data to the compression unit in the format that the compression unit requests. The DRAM controller also accepts data from the compression unit and stored them in the DRAM temporarily. In both DSC mode and Video mode, the DRAM controller is responsible to reorder the image data for appropriate JPEG compression format. Also it must decides the size for image in the variety of the operation modes.
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SPCA500A Digital Camera Chipset
If the DRAM is used as the storage element, the DRAM must enters self-refresh state when the camera is not in operation. This will save a lot of power. A register bit in the DRAM controller register set is dedicated to this function. To save image into the DRAM or unload the images from the DRAM, the micro-controller must set a set of range registers. They define the starting address and ending address of the saving/unloading area. The data is stored into (or read from) the DRAM in raster-scan order. Note that the DRAM controller restricts the DRAM range to be set based on a 4-words block. Only 4*N (the multiples of 4) are legal for the starting column address. And only 4N+3 is legal for the ending column address.
3.6. Embedded Micro Controller
The SPCA500A has integrated an 8032-compatible micro-controller, a serial communication port and a build-in 4Kx 8 SRAM. To simplify the firmware development, the users may disable the internal micro-controller and connect the SPCA500A to an external micro-controller.
Internal CPU connection
romwr cs0nn a16 psenn ale cpuad[7:0] cpua[15:8] romwr cs0nn a16 psen ale cpuad[7:0] cpua[15:8]
latch addr[15:8] addr[7:0] data[7:0]
p2
p0
gpio_4 augpio_0 augpio_5 psen ale gpio_0 gpio_1 gpio_2 gpio_3 gpio_5 gpio_6 gpio_7 augpio_1 augpio_4 augpio_6 augpio_7 p3_0 p3_1 p3_3 flashlight igbt_on gpio1 gpio2 di do pclk pwr1 request pwr2 pwr3 rxd txd int1nn
128K FLASH ROM
PPC CHIP
(from SPL15A) (to SPL15A) (from SPL15A) (to SPL15A)
For internal 8051 connection, the cpu read/write signals are not routed out of the 128-pin package. If using external SRAM, the shadow function for ISP is not supported.
External CPU connection
wrnn rdnn cs0nn a16 psenn ale cpuad[7:0] cpua[15:8] wrnn rdnn cs0nn a16 psen ale cpuad[7:0] cpua[15:8]
latch addr[14:8] data[7:0] addr[7:0] addr[15:8]
data[7:0]
ale p2 p0
augpio_5 augpio_0
PPC chip
gpio_2 gpio_3
ale p2 p0
psen
p3_6 p3_7
gpio_0 gpio_1 gpio_5 gpio_6 gpio_7 augpio_4
rom_wr_enn shadow_on di do pclk request (from SPL15A) (to SPL15A) (from SPL15A) (to SPL15A)
32K SRAM
128K FLASH ROM
WEB OEB
External 8051 p3_0 p3_1
txd rxd
For external CPU connection, gpio_3 and gpio_2 are used as read/write inputs from the external 8051
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p3_3 shadow_on psenn wrnn
int1nn
int0nn
rom_wr_en
wrnn
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SPCA500A Digital Camera Chipset
The micro-controller is similar to DS80C320(Dallas Semiconductor) in terms of hardware features and instruction cycle timing. However, there are some important differences between the micro-controller and the DS80C320 :
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Serial ports The micro-controller does not implement serial port framing error detection and does not implement slave address comparison for multiprocessor communications. Timer 2 The micro-controller does not implement timer2 down-counting mode or the down-count enable bit(T2MOD, bit0). The timer2 overflow output is active for one clock cycle. In the DS80C320, the timer2 overflow output is a square wave with a 50% duty cycle. Watchdog timer The micro-controller does not implement an internal watchdog timer. Power fail detector The micro-controller does not implement an internal power fail detector. Stop mode The micro-controller internal cycle counter is reset in stop mode. The micro-controller exits stop mode only when reset. Timed access protection The micro-controller does not implement timed access protection.
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T Serial communication port
The serial communication port is an optional function. It provides a serial communication between SPCA500A and the external LCD controller(User Interface controller). There are two modes in the serial communication port. The block diagram is shown below, where UI represents the User Interface controller and PPC represents SPCA500A :
z Master-slave mode(UI is master, PPC is slave) UI send one byte command to PPC first, then PPC processor will reply this command with multiple-
byte data(the protocol must be defined first). After the command protocol is finished, another command can be issued. Otherwise, this command will be queued.
z Slave request mode(PPC request to send command to UI) PPC make request signal (GPIO) pull high to inform UI that PPC want to send command to UI.
When UI receive this request, UI will finish the unfinished command if any command is still processing, then UI send out the special command(Grant request) to PPC. Thus, PPC will prepare the command for UI and pull the request signal to low, then UI will fetch the command and reply it.
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Serial Interface of PPC and UI
PCLK
SPCA500A Digital Camera Chipset
UI
(master)
PPC
(slave)
DI
DO REQ
PCLK DI/DO
start bit(2 bits)
data bit(8 bits)
stop bit(1 bit)
REQ DI
release-bus command
8032 put data on shift reg and pull REQ low
NOTE:
Tx device use PCLK rising edge to transmit data Rx device use PCLK falling edge to sample data PPC and UI are half-duplex
3.7. USB T USB Pipes and Vendor Command SPCA500A supports the following 6 USB pipes : Default pipe (EP0) : Process the standard commands and vendor commands. Video ISO-IN pipe (EP1) : Transmit Video image data (interface 0) BULK-IN pipe (EP2) : Upload still image to the PC (interface 1) BULK-OUT pipe (EP3) : Download still image and ROM code - for ISP function (interface 1) INTERRUPT-IN pipe (EP4) : Transmit device events (interface 1) Audio ISO-IN pipe (EP5) : Transmit audio data (interface 2) All standard commands, except the Get Descriptor command, are processed by hardware. For Get Descriptor command and vendor commands, the USB controller latches the 8-byte commands in the EP0 FIFO and interrupt the micro-controller. The micro-controller then read the 8-byte command, decode it, and prepare the appropriate data corresponding the command if necessary. The data, in any, is then sent to the USB bus by the USB controller.
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The alternative setting command for each interface is done by hardwire. However, there is a mechanism to inform firmware if the USB host changes the setting. The mechanism is described as follows : 1. Record the latest alternative setting. 2. Compare the latest setting (in USB side) with the previous one (in CPU side). 3. If the comparison is different, an interrupt will be asserted to inform the CPU. 4. The CPU writes the value of the alternative setting in USB side to that in CPU side.
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USB Vendor Command for Register Read/Write (for example) Command Read Write bmReqType 0C1 0x41 bRequest 0x00 0x00 wValue Reserved High byte : reserved low byte: write value wIndex Address Address wLength 1 0
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USB Vendor Command for Image Upload (for example) Command bmReqType 0x41 0x41 0x41 0xc1 bRequest 0x01 0x01 0x01 0x01 wValue Image index Image index Reserved Reserved wIndex 0x0000 0x0001 0x0002 0x0003 wLength 0x0000 0x0000 0x0000 0x0001
Get thumbnail Get image Get FAT Get status
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USB Video ISO-IN Packet Format For the video ISO-IN pipe (the EP1), the host may issue standard commands to change its maximum packet size. To achieve the optimal system performance, the user must adjust the alternative interface setting based on the image size and compression rate. The following table shows the maximum packet sizes for the available alternative interface settings. Alternative Interface Setting 0 1 2 3 4 5 6
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Maximum Packet Size (bytes) 0 128 384 512 640 768 896 Preliminary
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The size of each video ISO-IN packet is either maximum or zero. If the drop packet option is enabled, the packet size is only maximal. Three possible types of packets are described below : 1. Start of frame packet : The first byte must be 0xff and the second byte be 0x01. Byte 2 to byte 15 contain image information of the corresponding image frame. The padding byte field indicates the number of padding bytes of the previous packet. 2. Drop packet : The packet contains no data. This indicates there is not enough data for transmission. The packet is padded with all 0's after byte 3. 3. Image packet : If the first byte of the packet is not 0xff, then the packet is an image packet. The first byte is the image sequence byte. The rest are image data.
start of frame packet
0xff 0x01 padding byte low byte padding byte high byte camera operation mode image width image height image mode Q-table index Image frame sequence CDSP information GPIO AUGPIO reserved
byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 - 15
drop packet
0xff 0x00 padding byte low byte padding byte high byte
image packet
0x00 - 0xfe
image 0x00
image
Note : CDSP information bit 0 is "edge enhancement enable" corresponding to register 0x8156 bit 0. CDSP information bit 1 is "Gamma lookup table enable" corresponding to register 0x8156 bit 1. Camera operation mode corresponds to register 0x8000 Image width corresponds to register 0x8001 Image height corresponds to register 0x8002 Q-table index corresponds to register 0x8880 GPIO corresponds to register 0x8982 AUGPIO corresponds to register 0x8985 Image frame sequence is the count for transmitted image frames.
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SPCA500A Digital Camera Chipset
USB Bulk-IN Packet Format The maximum packet size is fixed at 64 bytes. The size of each Bulk-IN packet is either maximum or zero. Zero-padding is applied to the last packet to make the size maximum if necessary. USB Bulk-OUT Packet Format The maximum packet size is fixed at 64 bytes. The size of each Bulk-OUT packet must be maximal. USB Interrupt-IN Packet Format The maximum packet size is fixed at two bytes. The micro-controller must program the interrupt pipe registers (both register 0x8506 and 0x8507) after it detects a new event. The USB controller sends the interrupt data to the host only after register 0x8507 is written. USB Audio ISO-IN Packet Format The maximum packet size may be changed via standard USB commands. The size of each audio ISO-IN packet is either maximum or zero. The data in the packet is all audio data.
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3.8. Flash Memory The flash memory is used to store still image compression data and thumbnail image. The CPU can transfer command, address and data to the flash memory by the 8-bit I/O port. There are three operation modes for the CPU to read/write the flash memory : one is the direct mode, another is the FIFO mode and the other is pseudo DRAM mode. The ECC that is 22-bit code for every 256 bytes will be generated in the FIFO mode. The ECC generated by hardware can be read from the registers (3 bytes for 256 bytes/page and 6 bytes for 512 bytes/page). The read/write operation sequence is described as follows : 1. 2. 3. 4. 5. 6. 7. 8. set the flash memory chip enable set the flash memory command enable (0x8400) write command to the flash memory via the flash memory data register (0x8400) clear the flash memory command enable set the flash memory address enable write address to the flash memory via the flash memory data register (0x8400) clear the flash memory address enable wait the flash memory ready
Direct mode:
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9. read/write data from/to the flash memory via the flash memory data register(0x8400) 10. read/write additional data from/to the flash memory via the flash memory data register(0x8400) FIFO mode : 9. read/write data from/to the flash memory via the post buffer data register (0x8300) 10. read the ECC generated by hardware from the ECC registers 11. read/write additional data from/to the flash memory via the flash memory register (0x8400) Pseudo DMA mode : 9. read the post buffer and write to the flash memory or read the flash memory and write to the post buffer via the post buffer data register (0x8300) 10. read the ECC generated by hardware from the ECC registers 11. read/write additional data from/to the flash memory via the flash memory register (0x8400)
3.9. Post buffer T FIFO Control There are two 1k-byte deep FIFOs in the device to concurrently handle both incoming and outgoing data stream in various operation modes and to easily handle data for the USB host controller. Some detailed information about the FIFO is shown as follows : Video Camera Mode : When SPCA500A is operated as a PC camera, the "mode" field in the register (0x8000) must be set to the video camera mode (0x4). In this mode, the image data will be processed by the front end and then will be transmitted into the post buffer through DRAM. The data in the post buffer will be read by the USB host controller through the Bulk-IN pipe or ISO-IN pipe based on the setting at the "VidBulkEn" field in the register. The deep of post buffer is the same as the maximal packet size of the USB that is used to transfer the image data in this mode.
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Still Camera Mode : When SPCA500A is operated as a DSC camera, the "mode" field in the register (0x8000) must be set to the still camera mode (0x3). In this mode, the image data will be processed and then will be transmitted into the post buffer through DRAM. The data in the post buffer will be read by the CPU and written into flash memory by the pseudo DMA mode (1). The deep of post buffer is the same as the page size of flash memory in this mode.
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Upload Mode (1) :
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When SPCA500A wants to record sound into flash memory, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x1. In this mode, the CPU will read and process the audio data and then write into flash memory by the FIFO mode. The deep of post buffer is the same as the page size of flash memory in this mode.
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Upload Mode (2) : When SPCA500A wants to read data from flash memory and to transfer through the CPU, for example RS-232 port, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x2. In this mode, the CPU will read and process data from flash memory by the FIFO mode. The deep of post buffer is the same as the page size of flash memory in this mode. Upload Mode (3) : When SPCA500A wants to upload data from flash memory to the PC through the USB bus, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x3. In this mode, The data in flash memory will be read by the CPU and written into post buffer by the pseudo DMA mode (2). The data in the post buffer will be read through the Bulk-IN pipe by the USB host controller. The deep of post buffer is the same as the page size of flash memory in this mode.
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Upload Mode (4) : When the USB host wants to do loop-back test, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x4. The forward path is from the PC through Bulk-OUT pipe to the CPU and the backward path is from the CPU through Bulk-IN pipe to the PC. The backward path is supported in this mode and the forward path is supported in the next mode, Upload Mode (5). The deep of post buffer is 64 bytes in this mode. Upload Mode (5) : When the USB host wants to update the ROM code for the CPU on flash memory, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x5. The new ROM code is transmitted into post buffer from the PC through the Bulk-OUT pipe. Then the CPU reads the post buffer and update the ROM code on the flash memory. The deep of post buffer is 64 bytes in this mode.
T
T
Upload Mode (6) :
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When SPCA500A wants to read data from DRAM and to transfer through the CPU, for example RS232 port, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0X6. In this mode, the data is read from DRAM, transmitted into post buffer and then the CPU will read and process data from post buffer. In this mode, DRAM is as storage and the deep of post buffer is 64 bytes.
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Upload Mode (7) : When SPCA500A wants to read data from DRAM and to transfer to the PC through the USB Bulk-IN pipe, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x7. In this mode, the data be transmitted into the post buffer from DRAM. The data in the post buffer will be read through the BulkIN pipe by the USB host controller. In this mode, DRAM is as storage and the deep of post buffer is 64 bytes. Upload Mode (8) : This is a test mode. In this mode, the "mode" field in the register (0x8000) must be set to the upload mode (0x1) and the "OprMode" field in the register (0x8301) must be set to the value of 0x8. The CPU will write, read back and compare data through post buffer and the deep of post buffer is 64 bytes in this mode.
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Test Mode (0): This is a test mode. In this mode, the "PBTest" field in the register (0x8304) to the value of 0x01. In this mode, the data from DRAM will be transmitted into the post buffer. The data in the post buffer will be forced to read by the CPU and written into flash memory by the pseudo DMA mode (1). The deep of post buffer is the same as the page size of flash memory in this mode.
T
Test Mode (1) : This is a test mode. In this mode, the "PBTest" field in the register (0x8304) to the value of 0x02. In this mode, the data from DRAM will be transmitted into the post buffer. The data in the post buffer will be forced to read through the Bulk-IN pipe by the USB host controller. The deep of post buffer is 64 bytes in this mode.
T
Test Mode (2) : This is a test mode. In this mode, the "PBTest" field in the register (0x8304) to the value of 0x04. In this mode, the data from DRAM will be transmitted into the post buffer. The data in the post buffer will be forced to read through the ISO-IN pipe by the USB host controller. The deep of post buffer is the same as the maximal packet size of the USB that is used to transfer the image data in this mode.
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Preliminary
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SPCA500A Digital Camera Chipset
3.10. Audio The audio controller is fully compatible with the AC-97 specification. It provides a digital interface (AC-link) to access an AC-97 codec. The AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams, as well as control register accesses. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data stream, each with 20-bit sample resolution.
3.11. Power Control When SPCA500A is operated in the video camera mode or upload mode, its power is supplied by the USB bus. According to the USB specification 1.0, no USB device may require more than 100 mA when first attached, a configured bus-powered USB device attached to a self-powered hub may use up to 500 mA and all USB devices must support a suspended mode that requires less than 500 uA. When SPCA500A is operated in the still camera mode, the power is supplied by batteries. So the power control is quite important. Most major components, such as image sensor module, DRAM, flash memory and audio device, are power-off when they are not in operation. All the input and bidirectional signals connected to the chip must be pulled high or low either by internal resistors inside the chip or by external resistors on the PC board. It prevents these signals from floating. During suspend state, the clock is stopped and all GPIOs are set to the predefined states (high or low depending on the register settings). These GPIO's may be used to control the power switches on the board. SPCA500A enters suspend state on any one of the following two conditions. First, when SPCA500A has detected the USB bus is idle for more than 3 ms. Second, a power-down event is detected on an GPIO pin. Both of the suspend conditions may be enabled or disabled via corresponding registers (register 0x8013 bit 1:0). Once the suspend event is detected, the micro-controller performs the suspend procedure and then stop the oscillator of SPCA500A. SPCA500A exits suspend state when it detects a non-idle state on the USB bus. Another way to wake up the SPCA500A is activating a predefined wake up pin (a GPIO). The SPCA500A has a built-in resume counter to ensure it is not in operation until the clock is stable. The built-in micro-controller is reset automatically after resume is over.
3.12. Synchronous Serial Interfaces The Synchronous Serial Interfaces is used to program the peripheral IC. The write sequence : S Slave Address + wb ACKs Sub Address ACKs
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Data
ACKs P Preliminary
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The read sequence : S Slave Address + wb ACKs Sub Address ACKs Sr Slave Address + r Or S Slave Address + wb ACKs Sub Address ACKs S Slave Address + r ACKs Data ACKm ACKs Data ACKm
SPCA500A Digital Camera Chipset
P P P
Where S is start condition, ACKs is acknowledge from slave, P is stop, Sr is repeat start condition, and ACKm is acknowledge from master.
4. IO Trap Description
Trap Pin ma[0] The CPU selection 0: internal 1: external The CPU clock frequency selection 0: 12 MHz 1: 24 MHz The USB transceiver selection 0: internal 1: external Internal PLL for generating 48 MHz clock 0: disable 1: enable The input frequency division The feedback frequency division The test mode 0: normal 1: CPU 2: TG 3: CDSP 4: MEMC 5: JPEG 6: BUFUSB 7: Globe Internal pull-low Function Note
ma[1]
ma[2]
ma[3]
ma[5:4] ma[8:6] ma[11:9]
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5. Pin Assignment and Package T Pin Assignment
Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Name ovss1 ovdd1 cke sdclk md0 md1 md2 md3 md4 md5 md6 md7 prstnn dvss1 xtalin xtalout dvddpll md8 md9 md10 md11 md12 md13 md14 md15 ma[0] ma[1] ma[2] ma[3] ma[4] ma[5] ma[6] ma[7] ma[8] ovss2 ovdd2 ma[9] ma[10] ma[11] ma[12] ma[13] fmcenn fmrenn fmwenn fmwpnn fmrdy p0[0] p0[1] p0[2] p0[3] p0[4] p0[5] p0[6] Direction
PG PG O O IO IO IO IO IO IO IO IO I PG I O PG IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
SPCA500A Digital Camera Chipset
Memo
5V 5V 5V 5V 5V 5V 5V 5V 5V
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V 5V 5V 5V 5V 5V 5V 5V IO-trap IO-trap IO-trap IO-trap IO-trap IO-trap IO-trap IO-trap IO-trap
IO IO IO O O O O O O I IO IO IO IO IO IO IO
5V,IO-trap,testmode 5V,IO-trap, testmode 5V,IO-trap,testmode fmcle fmale
5V, external pull-up 5V 5V 5V 5V 5V 5V 5V
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54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 1999/10/05 Ver. 0.2 p0[7] dvss2 dvdd2 gpio[0] gpio[1] gpio[2] gpio[3] gpio[4] gpio[5] gpio[6] gpio[7] ale psenn ovss3 ovdd3 p2[0] p2[1] p2[2] p2[3] p2[4] p2[5] p2[6] p2[7] augpio[0] augpio[1] augpio[2] augpio[3] p3[3] augpio[4] augpio[5] augpio[6] augpio[7] dvss3 dvdd3 ccdrgb[0] ccdrgb[1] ccdrgb[2] ccdrgb[3] ccdrgb[4] ccdrgb[5] ccdrgb[6] ccdrgb[7] ccdrgb[8] ccdrgb[9] Suspend Uvdd Dm Dp Uvss Vtax Vtbx Vtdx Vhax Ofd Fr fh1 fh2
IO IO IO IO IO IO IO IO IO IO IO
SPCA500A Digital Camera Chipset
5V 5V,S 5V,S 5V,S (ext. cpu write) 5V,S(ext. cpu read) 5V,S(ROM write) 5V,S 5V,S 5V,S 5V 5V
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
I I I I I I I I I I O PG IO IO PG IO IO IO IO IO IO IO IO
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
5V,S (exthd) 5V,S (extvd)
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Preliminary
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IO 111 Load PG 112 tvss PG 113 tvdd IO 114 sck IO 115 sdi IO 116 pblk IO 117 rs IO 118 fs IO 119 fcds IO 120 adclp IO 121 bpx IO 122 adck PG 123 dvss4 PG 124 dvdd4 O 125 rasnn O 126 casnn O 127 mwenn O 128 moenndqm L: chip internal pull-low H: chip internal pull-high Z: chip does not drive/pull the pin C: customized on the board (pull-high or pull-low) P: the output enable is programmable via internal register 0: chip drive low 1: chip drive high 5V: 5-volt tolerant IO S: schmitt trigger
SPCA500A Digital Camera Chipset
(Serial clock) (Serial data, pull up ext)
CLKX1 output CLKX2 output 5V,CKx2 input 5V,CKx1 input
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Preliminary
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T
Pin Outline
SPCA500A Digital Camera Chipset
(8mA) (8mA) (8mA) (8mA) (4mA) (8mA) (8mA) (8mA) (4mA)
(4mA) (4mA) (4mA) (8mA) (8mA) (8mA) (4mA) (4mA) (4mA)
vtax vtbx vtdx vhax ofd fr fh1 fh2 load tvss tvdd sck sdi pblk rs fs fcds adclp bpx adck dvss4 dvdd4 rasnn casnn mwenn moenndqm
uvss dp dm uvdd suspend ccdrgb9 ccdrgb8 ccdrgb7 ccdrgb6 ccdrgb5 ccdrgb4 ccdrgb3 ccdrgb2 ccdrgb1 ccdrgb0 dvdd3 dvss3 augpio_7 augpio_6 augpio_5 augpio_4 p3_3 augpio_3 augpio_2 augpio_1 augpio_0 p2_7 p2_6 p2_5 p2_4 p2_3 p2_2 p2_1 p2_0 ovdd3 ovss3 psenn ale
1 0 2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 64 63 62 61
(ext_rd) (ext_wr)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
NNAAI nei naaiaeae
gpio_7 gpio_6 gpio_5 gpio_4 gpio_3 gpio_2 gpio_1 gpio_0 dvdd2 dvss2 p0_7 p0_6 p0_5 p0_4 p0_3 p0_2 p0_1 p0_0 fmrdy fmwpnn fmwenn fmrenn fmcenn m a 1 3 (fmale) m a 1 2 (fmcle) ma11
int1nn txd
rxd
OE E noaeoeooia eioaeoiai aaeii noaeoeooia OOA aaeii noaeoeooia E aoccaeo noaeoeooia
ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 md15 md14 md13 md12 md11 md10 md9 md8 dvdd1 xtalout xtalin dvss1 prstnn md7 md6 md5 md4 md3 md2 md1 md0 sdclk cke ovdd1 ovss1
ovdd2 ovss2
ma10 ma9
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Preliminary
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T
Package dimension
D D1 D2
SPCA500A Digital Camera Chipset
E
E1
E2
SUNPLUS SPCA500A
YYWW ABC
e
b
A2
A
Note : YYWW : Date Code, ABC : Internal Code
Symbol A A2 E E1 E2 D D1 D2 e b unit : millimeter
Min. 2.5 17.20 14.00 12.50 23.20 20.00 18.50 0.50 0.17
Nom. 2.72 17.20 14.00 12.50 23.20 20.00 18.50 0.50 0.20
Max. 3.4 2.9 17.20 14.00 12.50 23.20 20.00 18.50 0.50 0.27
1999/10/05 Ver. 0.2
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Preliminary

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